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  • Exam Number/Code : H12-891_V1.0-ENU
  • Exam Name : HCIE-Datacom V1.0
  • Questions and Answers : 260 Q&As
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NEW QUESTION: 1




Answer:
Explanation:


NEW QUESTION: 2
A customer has a multi-frame Synergy solution. The customer's Support team recently missed some important alerts in its Composer instance because each pair of Composers resides on a separate management network.
What should the customer do to minimize the risk of this reoccurring?
A. Implement HPE Synergy Global Dashboard
B. Implement HPE System insight Manager
C. Configure HPE Intelligent Management Center
D. Configure Remote Support
Answer: C

NEW QUESTION: 3
Which tow actions must be taken when an observable microservice application is developed? (Choose two.)
A. Deploy microservice to multiple datacenters.
B. Use distributed tracing techniques.
C. Know the state of a single instance of a single service.
D. Place "try/except" statement in code.
E. Place log statements in the code.
Answer: D,E

NEW QUESTION: 4
z13 Systemsプロセッサー装置(PU)チップの設計は、zEC12よりも拡張されています。
次のうちどれが改善を特徴付けるのですか?
A. z13ではzEC12と比較してキャッシュレベルのサイズが大きくなりました。
B. z13のプロセッササイクルタイムが高速です(zEC12の5.0 GHzではなく5.5 GHz)。
C. z13では1チップあたり最大6個のアクティブコア、zEC12では4個のアクティブコア。
D. すべてのコアで共有される改良された暗号化および圧縮エンジン
Answer: A
Explanation:
z13およびz13sの追加容量に貢献するのは、新しい命令、マルチスレッド化、および再設計されたより大きなキャッシュを含む、プロセッサー・チップ設計における多数の改善です。
Z13プロセッサ:
* L1キャッシュ
9 6 KB I-L1
1コアあたり1 28 KB D-L1
* L2キャッシュ
2 MB I-L2
コアあたり2 MB D-L2
L3キャッシュ64 MB共有
zEC12プロセッサー
L1キャッシュ64 + 96 KB /コア
L2キャッシュ1 + 1 MB /コア
L3キャッシュ48 MB /チップ
参考文献:
https://en.wikipedia.org/wiki/IBM_zEC12_(マイクロプロセッサ)
https://en.wikipedia.org/wiki/IBM_z13_(マイクロプロセッサ)

 

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